1. Field of the Invention
The present invention relates to storage interfaces in symmetrical multiprocessor systems, and more specifically, to a source synchronous transfer scheme that may increase the data rate over normal synchronous transfer methods.
2. Description of the Prior Art
In most general purpose, stored program, digital computers, it is desirable to have shared resources contained therein. Each of the shared resources may be designed to service a number of users. Possible shared resources may include a bus, a memory, a processor, or any other element within the computer system. The concept of utilizing shared resources has been used for several years to decrease the number of components within a computer system thereby increasing the cost effectiveness of the system. The use of shared resources also reduces the overall size and power requirements of the computer system.
Although these benefits can be substantial, shared resources may reduce the band pass of a system if not carefully used and designed. One reason for this is that only one of the users may use the shared resource at any given time. That is, the users must "share" the resource. Consistent therewith, computer designers must weigh the advantage of using a shared resource against the band pass limiting effect inherent therein. To increase the number of applications for shared resources and thus to take advantage of the benefits attributable thereto, computer designers have attempted to increase the band pass of shared resource designs.
One method for increasing the overall band pass of a shared resource design is to utilize priority schemes. For example, in a typical system, a number of processors may communicate with one another across a shared bi-directional bus. However, only one of the processors may use the shared bus at any given time. Therefore, the computer system must employ a mechanism for ensuring that only one processor has access to the shared bus at any given time while blocking access of the remaining processors.
Often, one or more of the processors may have a greater need to access the shared bus. One reason for this may be that one or more of the processors may be in the critical path of the computer system. If a processor is in the critical path of a computer system and it is not allowed to access the shared resource, the band pass of the entire computer system may suffer.
In a typical data processing system, there is a maximum of one data transfer per clock cycle. That is, data is typically transferred from a sending device to a receiving device on a leading or trailing edge of a system clock pulse. Thus, there is a direct relationship between the clock cycle time and the data transfer rate. Accordingly, data transfer rates are typically limited by the maximum clock rate of the system.
Several potential problems are encountered when increasing the maximum clock rate of the system. Transfers of data will typically occur between a transmitting and receiving component through two sets of latches. In order for the data to transfer successfully between the transmitting and receiving component, the data must traverse the path from the transmitting component latch to the receiving component latch within a set period of time, typically one clock cycle. Additionally the receiving latch requires the data to reach the input of the latch a certain period of time before the clock cycle occurs (typically referred to as "set-up" and "hold" times). Thus, timing constraints on the data transmittal path become more acute as the transfer clock rates are increased.